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e advance information april 1997 order number: 290542-003 n intel smartvoltage technology ? 5v or 12v program/erase ? 5v read operation n very high performance read ? 80 ns max. access time, ? 40 ns max. output enable time n low power consumption ? maximum 65 ma read current at 5v n x8/x16-selectable input/output bus ? high performance 16- or 32-bit cpus n optimized array blocking architecture ? one 16-kb protected boot block ? two 8-kb parameter blocks ? one 96-kb main block ? one 128-kb main block ? top or bottom boot locations n hardware-protection for boot block n software eeprom emulation with parameter blocks n automotive temperature operation ? -40c to +125c n extended cycling capability ? 30,000 block erase cycles for parameter blocks ? 1,000 block erase cycles for main blocks n automated word/byte program and block erase ? industry-standard command user interface ? status registers ? erase suspend capability n sram-compatible write interface n automatic power savings feature ? 1 ma typical i cc active current in static operation n reset/deep power-down input ? 0.2 a i cc typical ? provides reset for boot operations n hardware data protection feature ? program/erase lockout during power transitions n industry-standard surface mount packaging ? 44-lead psop: jedec rom compatible n etox? iv flash technology a28f200br-t/b 2-mbit (128k x 16, 256k x 8) smartvoltage boot block flash memory family automotive
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the a28f200br-t/b may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available upon request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation, 1996, 1997 cg-041493 *third-party brands and names are the property of their respective owners.
e a28f200br 3 advance information contents page page 1.0 product family overview.....................5 1.1 new features in the smartvoltage products ...............................5 1.2 main features ..............................................5 1.3 applications..................................................6 1.4 pinouts.........................................................6 1.5 pin descriptions ...........................................8 2.0 product descripton...............................9 2.1 memory organization...................................9 2.1.1 boot block .............................................9 2.1.2 parameter blocks ................................10 2.1.3 main blocks .........................................10 3.0 product family principles of operation ................................................10 3.1 bus operations ..........................................12 3.2 read operations ........................................12 3.2.1 read array ..........................................12 3.2.2 intelligent identifiers ............................12 3.3 write operations ........................................12 3.3.1 command user interface.....................12 3.3.2 status register....................................15 3.3.3 program mode.....................................16 3.3.4 erase mode .........................................17 3.4 boot block locking ....................................20 3.4.1 v pp = v il for complete protection .......20 3.4.2 wp# = v il for boot block locking .......21 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking .........................21 3.5 power consumption ...................................21 3.5.1 active power .......................................21 3.5.2 automatic power savings ....................21 3.5.3 standby power ....................................21 3.5.4 deep power-down mode.....................21 3.6 power-up operation...................................22 3.6.1 rp# connected to system reset ........22 3.7 power supply decoupling ..........................22 3.7.1 v pp trace on printed circuit boards ....22 3.7.2 v cc , v pp and rp# transitions .............22 4.0 absolute maximum ratings ................23 5.0 operating conditions ..........................24 5.1 v cc voltage................................................24 5.2 dc characteristics .....................................25 5.3 ac characteristics......................................29 appendix a: ordering information .................36 appendix b: additional information ...............37
a28f200br e 4 advance information revision history number description -001 original version -002 changed rp# ac characteristics changed v lko to 3.5v -003 parameter block cycling specification increased to 30,000 i ccd specification increased to 105 a i ccr specification increased to 65 ma t whax specification changed from 10 ns to 0 ns
e a28f200br 5 advance information 1.0 product family overview this datasheet contains the specifications for the automotive version of the 28f200br family of boot block flash memory devices. this device continues to offer the same functionality as earlier bx devices but adds the capability of performing program and erase operations with a 5v or 12v v pp . the a28f200br automatically senses which voltage is applied to the v pp pin and adjusts its operation accordingly. 1.1 new features in the smartvoltage products the new smartvoltage boot block flash memory family offers identical operation as the current bx/bl 12v program products, except for the differences listed below. all other functions are equivalent to current products, including signatures, write commands, and pinouts. wp# pin has replaced a du pin. see table 1 for details. 5v program/erase operation has been added that uses proven program and erase techniques with 5v 10% applied to v pp . if you are designing with existing bx 12v v pp boot block products today, you should provide the capability in your board design to upgrade to these new smartvoltage products. follow these guidelines to ensure compatibilty: 1. connect wp# (du on existing products) to a control signal, v cc or gnd. 2. if adding a switch on v pp for write protection, switch to gnd for complete write protection. 3. allow for connecting 5v to v pp instead of 12v, if desired. 1.2 main features intels smartvoltage technology provides the most flexible voltage solution in the industry. smartvoltage provides two discrete voltage supply pins, v cc for read operation, and v pp for program and erase operation. discrete supply pins allow system desi gners to use the optimal voltage levels for their design. for program and erase operations, 5v v pp operation eliminates the need for in system volt age converters, while 12v v pp operation provides faster program and erase for situations where 12v is available, such as manufacturing or designs where 12v is already available. the 28f200 boot block flash memory family is a very high-performance, 2-mbit (2,097,152 bit) flash memory family organized as either 256 kwords (131,072 words) of 16 bits each or 512 kbytes (262,144 bytes) of 8 bits each. separately erasable blo cks, including a hardware- lockable boot block (16,384 bytes), two parameter blocks (8, 192 bytes each) and main blo cks (one block of 98,304 bytes and one block of 131,072 bytes) define the boot block flash family architecture. see figure 3 for memory maps. each parameter block can be independently erased and programmed 10,000 times. each main block can be erased 1,000 times. the boot block is located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. the hardware-lockable boot block provides complete code security for the kernel code required for system initialization. locking and unlocking of the boot block is controlled by wp# and/or rp# (see section 3.4 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. the status register (sr) indicates the status of the wsm and whether it successfully completed the desired program or erase operation. program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the cui. data writes are performed in word or byte increments. each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. the 4-mbit smartvoltage boot block flash memory family is also designed with an automatic power
a28f200br e 6 advance information savings (aps) feature which minimizes system battery current drain, allowing for very low power designs. to provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memorys circuitry off. this mode is controlled by the rp# pin and its usage is discussed in section 3.5, along with other power consumption issues. additionally, the rp# pin provides protection against unwanted command writes due to invalid system bus c onditions that may occur during system reset and power-up/down sequences. also, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uniterrupted to the system com ponents, the flash memory could remain in a non-read mode, such as erase. consequently, the system reset pin should be tied to rp# to reset the memory to normal read mode upon activation of the reset pin. the byte-wide or word-wide input/output is controlled by the byte# pin. see table 1 for a detailed description of byte# operations, especially the usage of the dq 15 /a -1 pin. the 28f200 products are available in a rom/eprom-compatible pinout and housed in the 44-lead psop (plastic small outline) package. refer to the dc characteristics table, section 5.2 for complete current and voltage specifications. refer to the ac characteristics table, section 5.3, for read, program and erase performance specifications. 1.3 applications the 2-mbit boot block flash memory family combines high-density, low-power, high- performance, cost-effective flash memories with blocking and hardware protection capabilities. their flexibility and versatility reduce costs throughout the product life cycle. flash memory is ideal for just-in-time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. when the product is in the end-users hands, and updates or feature enhancements become necessary or mandatory, flash memory eliminates the need to replace an assembly. the update can be performed as part of routine maintenance operation by relatively unsophisticated technicians. the reliability of such a field upgrade is enhanced by a hardware-protected 16-kbyte boot block. if the protection methods are implemented in the circuit design, the boot block will be unchangeable. locating the boot-strap code in this area assures a fail-safe recovery from an update operation that failed to complete correctly. the two 8-kbyte parameter blocks allow modification of control algorithms to reflect changes in the process or device being controlled. a variety of software algorithms allow these two blocks to behave like a standard eeprom. intels boot block architecture provides a flexible voltage solution for the different design needs of various applications. the asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. the boot block provides a secure boot prom; the parameter blocks can emulate eeprom functionality for parameter store with proper software techniques; and the main blo cks provide code and data storage with access times fast enough to execute code in place, decreasing ram requirements. 1.4 pinouts intels smartvoltage boot block architecture provides upgrade paths in every package pinout to the 8-mbit density. the 28f200 44-lead psop pinout follows the industry standard rom/eprom pinout as shown in figure 2. pinouts for the corresponding 4-mbit and 8-mbit components are also provided for convenient reference. 2-mbit pinouts are given on the chip illustration in the center, with 2-mbit and 8-mbit pinouts going outward from the center.
e a28f200br 7 advance information a[1:17] cs# rd# wr# d[0:15] a[0:16] ce# oe# we# dq[0:15] intel386? ex microprocessor gpio gpio reset# pwrgood pld intel 28f200-t rp# v gpio reset# wp# byte# 5v 5v pp pld transceiver 0542-01 figure 1 . 28f200bx interface to intel386? microprocessor ab28f200 44-lead psop 0.525" x 1.110" top view gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 32 31 30 29 28 27 26 25 24 23 33 34 35 36 37 38 39 40 41 42 43 44 ce# wp# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 v pp nc ce# wp# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v pp gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 28f400 28f400 dq 15 -1 /a dq 15 -1 /a ce# gnd oe# a 7 a 5 a 6 a 4 a 3 a 2 a 1 a 0 dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v pp 28f800 gnd we# rp# byte# a 8 a 9 a 11 a 12 a 13 a 14 a 16 dq 7 dq 14 dq 6 dq 13 dq 12 dq 4 v cc dq 5 a 10 a 15 28f800 dq 15 -1 /a a 17 a 17 a 18 0542_02 note: pin 2 is du for bx 12v v pp versions. figure 2. 44-lead psop lead configuration for x8/x16 28f200 is compatible with 4 and 8 mbit.
a28f200br e 8 advance information 1.5 pin descriptions table 1. 28f200 pin descriptions symbol type name and function a 0 - a 16 input address inputs for memory addresses. addresses are internally latched during a write cycle. a 9 input address input: when a 9 is at v hh the signature mode is accessed. during this mode, a 0 decodes between the manufacturer and device ids. when byte# is at a logic low, only the lower byte of the signatures are read. dq 15 /a -1 is a dont care in the signature mode when byte# is low. dq 0 -dq 7 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched during the write cycle. outputs array, intelligent identifier and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. dq 8 -dq 15 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched during the write cycle. outputs array data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (byte# = 0). in the byte-wide mode dq 15 /a -1 becomes the lowest order address for data output on dq 0 -dq 7 . ce# input chip enable: activates the devices control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. if ce# and rp# are high, but not at a cmos high level, the standby current will increase due to current flow through the ce# and rp# input stages. oe# input output enable: enables the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command register and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. rp# input reset/deep power-down: uses three voltage levels (v il , v ih , and v hh ) to control two different functions: reset/deep power-down mode and boot block unlocking. it is backwards-compatible with the 28f200bx/bl. when rp# is at logic low, the device is in reset/deep power-down mode , which puts the outputs at high-z, resets the write state machine, and draws minimum current. when rp# is at logic high, the device is in standard operation . when rp# transitions from logic-low to logic-high, the device defaults to the read array mode. when rp# is at v hh , the boot block is unlocked and can be programmed or erased. this overides any control from the wp# input.
e a28f200br 9 advance information table 1. 28f200 pin descriptions (continued) symbol type name and function wp# input write protect: provides a method for unlocking the boot block in a system without a 12v supply. when wp# is at logic low, the boot block is locked , preventing program and erase operations to the boot block. if a program or erase operation is attempted on the boot block when wp# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the status register to indicate the operation failed. when wp# is at logic high, the boot block is unlocked and can be programmed or erased. note: this feature is overridden and the boot block unlocked when rp# is at v hh . see section 3.4 for details on write protection. byte# input byte# enable: controls whether the device operates in the byte-wide (x8) mode or the word (x16) mode. the byte# input must be controlled at cmos levels to meet the cmos current specification in the standby mode. when byte# is at logic low, the byte-wide mode is enabled. a 19-bit address is applied on a -1 to a 17 , and 8 bits of data is read and written on dq 0 -dq 7 . when byte# is at logic high, the word-wide mode is enable. an 18-bit address is applied on a 0 to a 17 and 16 bits of data is read and written on dq 0 - dq 15 . v cc device power supply: 5.0v 10% v pp program/erase power supply: for erasing memory array blocks or programming data in each block, a voltage either of 5v 10% or 12v 5% must be applied to this pin. when v pp < v ppl k all blocks are locked and protected against program and erase commands. gnd ground: for all internal circuitry. nc no connect: pin may be driven or left floating. 2.0 product descripton 2.1 memory blocking organization this product family features an asymmetrically- blocked architecture enhancing system memory integration. each block can be erased independently of the others up to 10,000 times. the block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. for the address locations of the blo cks, see the memory maps in figure 3. 2.1.1 one 16-kb boot block the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller- based system. the 16-kbyte (16, 384 bytes) boot block is located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map to accommodate different microprocessor protocols for boot code location. this boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental erasure. the protection of the boot block is controlled using a combination of the v pp , rp#, and wp# pins, as is detailed in table 8.
a28f200br e 10 advance information 2.1.2 two 8-kb parameter blocks the boot block architecture includes parameter blocks to facilitate stor age of frequently updated small parameters that would normally require an eeprom. by using software techniques, the byte- rewrite functionality of eeproms can be emulated. these techniques are detailed in intels ap-604, using intels boot block flash memory parameter blocks to replace eeprom. each boot block component contains two parameter blo cks of eight kbytes (8,192 bytes) each. the parameter blocks are not write-protectable. 2.1.3 one 96-kb + three 128-kb main blocks after the allocation of address space to the boot and parameter blo cks, the remai nder is divided into main blocks for data or c ode storage. each 2-mbit device contains one 96-kbyte (98,304 byte) block and one 128-kbyte (131,072 byte) block. see the memory maps for each device for more information. 3.0 product family principles of operation flash memory augments eprom functionality with in-circuit electrical program and erase. the boot block flash family utilizes a command user interface (cui and automated algorithms to simplify program and erase operations. the cui allows for 100% ttl-level control inputs, fixed power supplies during erasure and programming, and maximum eprom compatibility. when v pp < v pplk , the device will only successfully execute the following commands: read array, read status register, clear status register and intelligent identifier mode. the device provides standard eprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the cui or through the standard eprom a 9 high voltage access (v id ) for prom programming equipment. the same eprom read, standby and output disable functions are available when 5v or 12v is applied to the v pp pin. in addition, 5v or 12v on v pp allows program and erase of the device. all functions associated with altering memory contents: program and erase, intelligent identifier read, and read status are accessed via the cui. the purpose of the write state machine (wsm) is to completely automate the programming and erasure of the device. the wsm will begin operation upon receipt of a signal from the cui and will report status back through a status register. the cui will handle the we# interface to the data and address latches, as well as system software requests for status while the wsm is in operation. 28f200-b 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 00000h 0ffffh 10000h 1bfffh 1c000h 1cfffh 1d000h 1dfffh 1e000h 1ffffh 28f200-t 128-kbyte main block 8-kbyte parameter block 16-kbyte boot block 8-kbyte parameter block 96-kbyte main block 1ffffh 10000h 0ffffh 04000h 03fffh 03000h 02fffh 02000h 01fffh 00000h 0542-03 figure 3. 28f200-t/b memory maps
e a28f200br 11 advance information table 2. bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce# oe# we# a 9 a 0 v pp dq 0-15 read 1,2,3 v ih v il v il v ih xxx d out output disable v ih v il v ih v ih x x x high z standby v ih v ih x x x x x high z deep power-down 9 v il x x x x x x high z intelligent identifier (mfr) 4 v ih v il v il v ih v id v il x 0089 h intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x see table 4 write 6,7,8 v ih v il v ih v il xxx d in table 3. bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce# oe# we# a 9 a 0 a -1 v pp dq 0-7 dq 8-14 read 1,2,3 v ih v il v il v ih xxxxd out high z output disable v ih v il v ih v ih x x x x high z high z standby v ih v ih x x x x x x high z high z deep power- down 9v il x x x x x x x high z high z intelligent identifier (mfr) 4v ih v il v il v ih v id v il x x 89h high z intelligent identifier (device) 4,5 v ih v il v il v ih v id v ih x x see table 4 high z write 6,7,8 v ih v il v ih v il xxxxd in high z notes: 1. refer to dc characteristics. 2. x can be v il , v ih for control pins and addresses, v pplk or v pph for v pp . 3. see dc characteristics for v pplk , v pph 1, v pph 2, v hh , v id voltages. 4. manufacturer and device codes may also be accessed via a cui write sequence, a 1 -a 17 = x, a 1 -a 18 = x. 5. see table 4 of device ids. 6. refer to table 5 for valid d in during a write operation. 7. command writes for block erase or word/byteprogram are only executed when v pp = v pph 1 or v pph 2. 8. to program or erase the boot block, hold rp# at v hh or wp# at v ih . 9. rp# must be at gnd 0.2v to meet the maximum deep power-down current specified.
a28f200br e 12 advance information 3.1 bus operations flash memory reads, erases and programs in- system via the local cpu. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. these bus operations are summarized in tables 2 and 3. 3.2 read operations the boot block flash device has three user read modes: array, intelligent identifier, and status register. status register read mode will be discussed, in detail, in section 3.3.2. 3.2.1 read array when rp# transitions from v il (reset) to v ih , the device will be in the read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any commands being written to the cui. when the device is in the read array mode, five control signals must be controlled to obtain data at the outputs. we# must be logic high (v ih ) ce# must be logic low (v il ) oe must be logic low (v il ) rp# must be logic high (v ih ) byte# must be logic high or logic low. in addition, the address of the desired location must be applied to the address pins. refer to figures 10 and 11 for the exact sequence and timing of these signals. if the device is not in read array mode, as would be the case after a program or erase operation, the read mode command (ffh) must be written to the cui before reads can take place. 3.2.1.1 output control with oe# at logic-high level (v ih ), the output from the device is disabled and data input/output pins (dq[0:15] or dq[0:7]) are tri-stated. 3.2.1.2 input control with we# at logic-high level (v ih ), input to the device is disabled. 3.2.2 intelligent identifiers the intelligent identifiers of the smartvoltage boot block components are identical to the boot block products that operate only at 12v v pp . the manufacturer and device codes are read via the cui or by taking the a 9 pin to v id . writing 90h to the cui places the device into intelligent identifier read mode. in this mode, a 0 = 0 outputs the manufacturers identification code and a 0 = 1 outputs the device code. when byte# is at a logic low, only the lower byte of the above signatures is read and dq 15 /a -1 is a dont care during intelligent identifier mode. see the table below for product signatures. a read array command must be written to the memory to return to the read array mode. table 4. intelligent identifier table product mfr. id device id -t (top boot) -b (bottom boot) 28f200 0089 h 2274 h 2275 h 3.3 write operations 3.3.1 command user interface (cui) the command user interface (cui) serves as the interface between the microprocessor and the internal chip controller. commands are written to the cui using standard microprocessor write timings. the available commands are read array, read intelligent identifier, read status register, clear status register, program and erase (summarized in table s 5 and 6). for read commands, the cui points the read path at either the array, the intelligent identifier, or the status register depending on the command received. for program or erase commands, the cui informs the write state machine (wsm) that a program or erase has been requested. during the execution of a program command, the wsm will control the programming sequences and the cui will only respond to status reads. during an erase cycle, the
e a28f200br 13 advance information cui will respond to status reads and erase suspend. after the wsm has completed its task, it will set the wsm status bit to a 1, which will also allow the cui to respond to its full command set. note that after the wsm has returned control to the cui, the cui will stay in the current command state until it receives another command. 3.3.1.1 command function description device operations are selected by writing specific commands into the cui. table 5 defines the available commands. table 5. command set codes and corresponding device mode command codes device mode 00 invalid reserved 10 alternate program set- up 20 erase set-up 40 program set-up 50 clear status register 70 read status register 90 intelligent identifier b0 erase suspend d0 erase resume/erase confirm ff read array invalid/reserved these are unassigned commands and should not be used. intel reserves the right to redefine these codes for future functions. read array (ffh) this single write cycle comm and points the read path at the array. if the host cpu performs a ce#/oe#-controlled read immediately following a two-write sequence that started the wsm, then the device will output status register contents. if the read array command is given after the erase setup command, the device will reset to read the array. a two read array command sequence (ffh) is required to reset to read array after the program setup command. intelligent identifier (90h) after this command is executed, the cui points the output path to the intelligent identifier circuits. only intelligent identifier values at addresses 0 and 1 can be read (only address a 0 is used in this mode, all other address inputs are ignored). read status register (70h) this is one of the two commands that is executable while the wsm is operating. after this command is written, a read of the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after program or erase has completed. clear status register (50h) the wsm can only set the program status and erase status bits in the status register to 1, it cannot clear them to 0. two reasons exist for operating the status register in this fashion. the first is synchronization. since the wsm does not know when the host cpu has read the status register, it would not know when to clear the status bits. secondly, if the cpu is programming a string of bytes, it may be more efficient to query the status register after programming the string. thus, if any errors exist while programming the string, the status register will return the accumulated error status. program setup (40h or 10h) this command simply sets the cui into a state such that the next write will load the address and data registers. after this command is executed, the outputs default to the status register. a two read array command sequence (ffh) is required to reset to read array after the program setup command.
a28f200br e 14 advance information table 6. command bus definitions notes first bus cycle second bus cycle command 8 oper addr data oper addr data read array 1 write x ffh intelligent identifier 2,4 write x 90h read ia iid read status register 3 write x 70h read x srd clear status register write x 50h word/byte program 6,7 write pa 40h write pa pd alternate word/byte program 6,7 write pa 10h write pa pd block erase/confirm 5 write ba 20h write ba d0h erase suspend/resume write x b0h write x d0h address data ba= block address srd= status register data ia= identifier address iid= identifier data pa= program address pd= program data x= dont care notes: 1. bus operations are defined in tables 2 and 3. 2. ia = identifier address: a 0 =0 for manufacturer code, a 0 =1 for device code. 3. srd - data read from status register. 4. iid = intelligent identifier data. following the intelligent identifier command, two read operations access manufacturer and device codes. 5. ba = address within the block being erased. 6. pa = address to be programmed. pd = data to be programmed at location wd. 7. either 40h or 10h commands is valid. 8. when writing commands to the device, the upper data bus [dq 8 -dq 15 ] = x (28f200 only) which is either v cc or v ss , to minimize current draw. program the second write after the program setup command, will latch addresses and data. also, the cui initiates the wsm to begin execution of the program algorithm. the device outputs status register data when oe# is enabled. a read array command is required after programming, to read array data. erase setup (20h) prepares the cui for the erase confirm command. no other action is taken. if the next command is not an erase confirm command, then the cui will set both the program status and erase status bits of the status register to a 1, place the device into the read status register state, and wait for another command.
e a28f200br 15 advance information erase confirm (d0h) if the previous command was an erase setup command, then the cui will enable the wsm to erase, at the same time closing the address and data latches, and respond only to the read status register and erase suspend commands. while the wsm is executing, the device will output status register data when oe# is toggled low. status register data can only be updated by toggling either oe# or ce# low. erase suspend (b0h) this command is only valid while the wsm is executing an erase operation, and therefore will only be responded to during an erase operation. after this command has been executed, the cui will set an output that directs the wsm to suspend erase operations, and then respond only to read status register or to the erase resume commands. once the wsm has reached the suspend state, it will set an output into the cui which allows the cui to respond to the read array, read status register, and erase resume commands. in this mode, the cui will not respond to any other commands. the wsm will also set the wsm status bit to a 1. the wsm will continue to run, idling in the suspend state, regardless of the state of all input control pins except rp#, which will immediately shut down the wsm and the remainder of the chip, if it is made active. during a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. erase resume (d0h) this command will cause the cui to clear the suspend state and clear the wsm status bit to a 0, but only if an erase suspend command was previously issued. erase resume will not have any effect under any other conditions. 3.3.2 status register the device contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. the status register may be read at any time by writing the read status command to the cui. after writing this command, all subsequent read operations output data from the status register until another command is written to the cui. a read array command must be written to the cui to return to the read array mode. the status register bits are output on dq[0:7], whether the device is in the byte-wide (x8) or word- wide (x16) mode. in the word-wide mode the upper byte, dq[8:15], is set to 00h during a read status command. in the byte-wide mode, dq[8:14] are tri- stated and dq 15 /a -1 retains the low order address function. important: the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last in the read cycle. this prevents possible bus errors which might occur if the contents of the status register change while reading the status register. ce# or oe# must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident from the status register. when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the desired operation. 3.3.2.1 clearing the status register the wsm sets status bits 3 through 7 to 1, and clears bits 6 and 7 to 0, but cannot clear status bits 3 through 5 to 0. bits 3 through 5 can only be cleared by the controlling cpu through the use of the clear status register command. these bits can indicate various error conditions. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in s equence). the status register may then be read to determine if an error occurred during that programming or erasure series. this adds flexibility to the way the device may be programmed or erased. to clear the status register, the clear status register command is written to the cui. then, any other command may be issued to the cui. note, again, that before a read cycle can be initiated, a r ead array command must be written to the cui to specify whether the read data is to come from the memory array, status register, or intelligent identifier.
a28f200br e 16 advance information 3.3.3 program mode programing is executed using a two-write sequence. the program setup command is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to: 1. program the desired bits of the addressed memory word or byte. 2. verify that the desired bits are sufficiently programmed. programming of the memory results in specific bits within a byte or word being changed to a 0. if the user attempts to program 1s, there will be no change of the memory cell content and no error occurs. similar to erasure, the status register indicates whether programming is complete. while the program sequence is executing, bit 7 of the status register is a 0. the status register can be polled by toggling either ce# or oe# to determine when the program sequence is complete. only the read status register command is valid while programming is active. table 7. status register bit definition wsms ess es dws vpps r r r 76543210 notes: sr.7 =write state machine status (wsms) 1 = ready 0 = busy write state machine bit must first be checked to determine byte/word program or block erase completion, before the program or erase status bits are checked for success. sr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status 1 = error in block erasure 0 = successful block erase when this bit is set to 1, wsm has applied the maximum number of erase pulses to the block and is still unable to successfully verify block erasure. sr.4 = program status 1 = error in byte/word program 0 = successful byte/word program when this bit is set to 1, wsm has attempted but failed to program a byte or word. sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the byte program or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feedback between v pplk and v pph . sr.2Csr.0 = reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register.
e a28f200br 17 advance information when programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. if bit 3 is set to a 1, then v pp was not within acceptable limits, and the wsm did not execute the programming sequence. if the program operation fails, bit 4 of the status register will be set within 3.3 ms as determined by the timeout of the wsm. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, reads from the memory array, status register, or intelligent identifier cannot be accomplished until the cui is given the read array command. 3.3.4 erase mode erasure of a single block is initiated by writing the erase setup and erase confirm commands to the cui, along with the addresses identifying the block to be erased. these addresses are latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. the wsm will execute a sequence of internally timed events to: 1. program all bits within the block to 0. 2. verify that all bits within the block are sufficiently programmed to 0. 3. erase all bits within the block. 4. verify that all bits within the block are sufficiently erased. while the erase sequence is executing, bit 7 of the status register is a 0. when the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. if the erase operation was unsuccessful, bit 5 of the status register will be set to a 1, indicating an erase failure. if v pp was not within acceptable limits after the erase confirm command is issued, the wsm will not execute an erase sequence; instead, bit 5 of the status register is set to a 1 to indicate an erase failure, and bit 3 is set to a 1 to identify that v pp supply voltage was not within acceptable limits. the status register should be cleared before attempting the next operation. any cui instruction can follow after erasure is completed; however, reads from the memory array, status register, or intelligent identifier cannot be accomplished until the cui is given the read array command. 3.3.4.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase-sequence interruption in order to read data from another block of the memory. once the erase sequence is started, writing the erase suspend command to the cui requests that the wsm pause the erase sequence at a pre-determined point in the erase algorithm. the status register must then be read to determine if the erase operation has been suspended. at this point, a read array command can be written to the cui in order to read data from blo cks other than that which is being suspended. the only other valid command at this time is the erase resume command or read status register command. during erase suspend mode, the chip can go into a pseudo-standby mode by taking ce# to v ih , which reduces active current draw. to resume the erase operation, the chip must be enabled by taking ce# to v il , then issuing the erase resume command. when the erase resume command is given, the wsm will continue with the erase sequence and complete erasing the block. as with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue.
a28f200br e 18 advance information sr.7 = 1 ? no yes start write 40h, word/byte address write word/byte data/address full status check if desired word/byte program complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error bus operation standby standby check sr.3 1 = v pp low detect sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.4 is only cleared by the clear status register command, in cases where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write setup program data = data to program addr = location to program read data = 40h addr = word/byte to program check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent word/byte program operations. sr full status check can be done after each word/byte program, or after a sequence of word/byte programs. write ffh after the last program operation to reset device to read array mode. standby sr.3= sr.4 = word/byte program error word/byte program successful check sr.4 1 = word/byte program error program status register data toggle ce# or oe# to update srd. command comments 0542_04 figure 4. automated word/byte programming flowchart
e a28f200br 19 advance information sr.7 = 0 1 start write 20h, block address write d0h and block address full status check if desired block erase complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error suspend erase suspend erase loop yes no 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = block erase error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby check sr.3 1 = v low detect sr.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.5 is only cleared by the clear status register command, in cases where multiple blocks are erase before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = block erase error standby bus operation command comments write write erase setup read data = 20h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. status register data toggle ce# or oe# to update status register standby erase confirm data = d0h addr = within block to be erased block erase successful pp 0542_05 figure 5. automated block erase flowchart
a28f200br e 20 advance information sr.7 = 0 1 start write b0h read status register write d0h erase resumed bus operation command comments write erase suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data toggle ce# or oe# to update srd. addr = x standby csr.6 = write ffh read array data done reading erase completed write ffh read array data yes no 0 1 check sr.6 1 = erase suspended 0 = erase completed standby data = ffh addr = x write read array data from block other than the one being erased. read data = d0h addr = x write read array erase resume 0542_06 figure 6. erase suspend/resume flowchart 3.4 boot block locking the boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blo cks are programmed and erased independently as necessary. only the boot block can be locked independently from the other blocks. 3.4.1 v pp = v il for complete protection for complete write protection of all blocks in the flash device, the v pp programming voltage can be held low. when v pp is below v pplk , any program or erase operation will result in a error in the status register.
e a28f200br 21 advance information 3.4.2 wp# = v il for boot block locking when wp# = v il , the boot block is locked and any program or erase operation will result in an error in the status register. all other blocks remain unlocked in this condition and can be programmed or erased normally. note that this feature is overridden and the boot block unlocked when rp# = v hh . 3.4.3 rp# = v hh or wp# = v ih for boot block unlocking two methods can be used to unlock the boot block: 1. wp# = v ih 2. rp# = v hh if both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. the truth table, table 8, clearly defines the write protection methods. table 8. write protection truth table for smartvoltage boot block family v pp rp# wp# write protection provided v il x x all blocks locked 3 v pplk v il x all blocks locked (reset) 3 v pplk v hh x all blocks unlocked 3 v pplk v ih v il boot block locked 3 v pplk v ih v ih all blocks unlocked 3.5 power consumption 3.5.1 active power with ce# at a logic-low level and rp# at a logic- high level, the device is placed in the active mode. refer to the dc characteristics table for i cc current values. 3.5.2 automatic power savings (aps) automatic power savings (aps) is a low-power feature during active mode of operation. the boot block flash memory family incorporates power reduction control (prc) circuitry which allows the device to put itself into a low current state when it is not being accessed. after data is read from the memory array, prc logic controls the devices power consumption by entering the aps mode where typical i cc current is less than 1 ma. the device stays in this static state with outputs valid until a new location is read. 3.5.3 standby power with ce# at logic-high level (v ih ), and the cui in read mode, the memory is placed in standby mode. the standby operation disables much of the devices circuitry and substantially reduces device power consumption. the outputs (dq[0:15] or dq[0:7]) are placed in a high-impedance state independent of the status of the oe# signal. when ce# is at logic-high level during erase or program functions, the devices will continue to perform the erase or program function and consume erase or program active power until erase or program is completed. 3.5.4 deep power-down mode the smartvoltage boot block family supports a low typical i cc in deep power-down mode. the device has a rp# pin which places the device in the deep power-down mode. when rp# is at a logic-low (gnd 0.2v), all circuits are turned off in order to save power. (note: byte# pin must be at cmos levels to achieve the most deep power-down current savings.) during read modes, the rp# pin going low de- selects the memory and places the output drivers in a high impedance state. recovery from the deep power-down state, requires a minimum access time of t phqv . (see the ac characteristics table for specification numbers.) during erase or program modes, rp# low will abort either erase or program operation. the contents of the memory are no longer valid as the data has been corrupted by the rp# function. as in the read mode above, all internal circuitry is turned off to achieve the power savings. rp# transitions to v il , or turning power off to the device will clear the status register.
a28f200br e 22 advance information 3.6 power-up operation the device is designed to offer protection against accidental block erasure or programming during power transitions. upon power-up, the device is indifferent as to which power supply, v pp or v cc , powers-up first. power supply sequencing is not required. a system desi gner must guard against spurious programming for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. finally the device is disabled until rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rp# connected to system powerg ood) during power up/down, invalid bus conditions that may occur can be masked. this feature provides yet another level of memory protection. 3.6.1 rp# connected to system reset the use of rp# during system reset is important with automated program/erase devices. when the system comes out of reset it expects to r ead from the flash memory. automated flash memories provide status information when accessed during program/erase modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization would not occur because the flash memory would be providing the status information instead of array data. intels flash memories allow proper cpu initialization following a system reset thr ough the use of the rp# input. in this application rp# is controlled by the same reset# signal that resets the system cpu. 3.7 power supply decoupling flash memorys power switching characteristics require careful device decoupling methods. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. active current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high frequency, inherently low inductance capacitors should be placed as close as possible to the package leads. 3.7.1 v pp trace on printed circuit boards writing to flash memories while they reside in the target system, r equires special consideration of the v pp power supply trace by the printed circuit board designer. the v pp pin supplies the flash memory cells current for programming and erasing. one should use similar trace widths and layout considerations given to the v cc power supply trace. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 3.7.2 v cc , v pp and rp# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from deep power-down mode, or after v cc transitions above v lko (lockout voltage), is read array mode. after any word/byte program or block erase operation is complete and even after v pp transitions down to v pplk , the cui must be reset to read array mode via the read array command when accesses to the flash memory are desired.
e a28f200br 23 advance information 4.0 absolute maximum ratings* operating temperature during read ........................... -40c to +125c during block erase and word/byte program ......... -40c to +125c temperature under bias ........ -40c to +125c storage temperature.................... -65c to +125c voltage on any pin (except v cc , v pp , a 9 and rp#) with respect to gnd .............. -2.0v to +7.0v (1) voltage on pin rp# or pin a 9 with respect to gnd .......... -2.0v to +13.5v (1,2) v pp program voltage with respect to gnd during block erase and word/byte program ........... -2.0v to +14.0v (1,2) v cc supply voltage with respect to gnd .............. -2.0v to +7.0v (1) output short circuit current....................100 ma (3) notice: this datasheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0v for periods <20ns. maximum dc voltage on rp# or a 9 may overshoot to 13.5v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time.
a28f200br e 24 advance information 5.0 operating conditions table 9. temperature and v cc operating conditions symbol parameter notes min max units t a operating temperature -40 +125 c v cc v cc supply voltage (10%) 4.50 5.50 volts 5.1 applying v cc voltages if the v cc ramp rate is greater than 0.01 v/s, a delay of 2 s is required before any device operation can be initiated. this includes array or status read, command writes and program or erase operations. the 2 s are measure beginning from the time v cc reaches v ccmin (4.5v). this delay is not tied to the operation of the reset input. it is recommended that the device be held in reset (rp# = gnd) while v cc is less than v ccmin . if the v cc ramp rate is less than 0.01 v/s, no delay is required once v cc has reached v ccmin . v cc ramp rate required timing 1v/100 m s no delay required. > 1v/100 m s a delay time of 2 m s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. this delay is measured beginning from the time v cc reaches v ccmin (4.5v for 5v operation). notes: 1. these requirements must be strictly followed to guarantee all other read and write specifications. 2. any time the v cc supply drops below v ccmin , the chip may be reset, aborting any operations pending or in progress. 3. these guidelines must be followed for any v cc transition from gnd.
e a28f200br 25 advance information 5.2 dc characteristics table 10. dc characteristics: automotive temperature operation symbol parameter notes min typ max unit test conditions i il input load current 1 5.0 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,3 0.8 2.5 ma v cc = v cc max ce# = rp# = byte# = v ih 70 250 a v cc = v cc max ce# = rp# = wp# = v cc 0.2v i ccd v cc deep power-down current 1 0.2 105 a v cc = v cc max v in = v cc or gnd rp# = gnd 0.2v i ccr v cc read current for word or byte 1,5,6 50 65 ma cmos v cc = v cc max ce = v il f = 10 mhz (5v) 5 mhz (3.3v) i out = 0 ma inputs = gnd 0.2v or v cc 0.2v 55 70 ma ttl v cc = v cc max ce# = v il f = 10 mhz i out = 0 ma inputs = v il or v ih i ccw v cc program current for word or byte 1,4 25 50 ma program in progress v pp = v pph 1 (at 5v) 20 45 ma program in progress v pp = v pph 2 (at 12v)
a28f200br e 26 advance information table 10. dc characteristics: automotive temperature operation (continued) symbol parameter notes min typ max unit test conditions i cce v cc erase current 1,4 22 45 ma block erase in progress v pp = v pph 1 (at 5v) 18 40 ma block erase in progress v pp = v pph 2 (at 12v) i cces v cc erase suspend current 1,2 5 12.0 ma ce# = v ih block erase suspend v pp = v pph 1 (at 5v) i pps v pp standby current 1 5 15 a v pp v cc i ppd v pp deep power-down current 1 0.2 10 a rp# = gnd 0.2v i ppr v pp read current 1 50 200 a v pp > v cc i ppw v pp program current for word or byte 11330ma v pp = v pph program in progress v pp = v pph 1 (at 5v) 825ma v pp = v pph program in progress v pp = v pph 2 (at 12v) i ppe v pp erase current 1 15 25 ma v pp = v pph block erase in progress v pp = v pph 1 (at 5v) 10 20 ma v pp = v pph block erase in progress v pp =v pph 2 (at 12v) i ppes v pp erase suspend current 1 50 200 a v pp = v pph block erase suspend in progress i rp# rp# boot block unlock current 1,4 500 a rp# = v hh v pp = 12v i id a 9 intelligent identifier current 1,4 500 a a 9 = v id v id a 9 intelligent identifier voltage 11.4 12.6 v v il input low voltage -0.5 0.8 v
e a28f200br 27 advance information table 10. dc characteristics: automotive temperature operation (continued) symbol parameter notes min typ max unit test conditions v ih input high voltage 2.0 v cc 0.5v v v ol output low voltage (ttl) 0.45 v v cc = v cc min i ol = 5.8 ma v pp =12v v oh 1 output high voltage (ttl) 2.4 v v cc = v cc min i oh = -1.5 ma v oh 2 output high voltage (cmos) v cc - .4v v v cc = v cc min i oh = -100 a v pplk v pp lock-out voltage 3 0.0 1.5 v complete write protection v pph 1 v pp (program/ erase operations) 4.5 5.5 v v pp at 5v v pph 2 v pp (program/ erase operations) 11.4 12.6 v v pp at 12v v lko v cc program/erase lock voltage 2.0 v v pp = 12v v hh rp# unlock voltage 11.4 12.6 v boot block program/erase v pp = 12v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, t = 25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device de-selected. if the devices is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte program operations are inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih .
a28f200br e 28 advance information table 11. capacitance (t a -25c, f = 1 mhz) symbol parameter note typ max unit conditions c in input capacitance 4 6 8 pf v in = 0v c out output capacitance 4 10 12 pf v out = 0v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, t = +25c. these currents are valid for all product versions (packages and speeds). 2. i cces is specified with the device de-selected. if the devices is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases and word/byte program operations are inhibited when v pp = v pplk , and not guaranteed in the range between v pph 1 and v pplk . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to less than 1 ma typical, in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0542-08 figure 7. 5v inputs and measurement points c l ou t v cc 585 w 394 w device under test 0538-09 note: c l = 100 pf, includes jig capacitance figure 8. 5v standard test configuration
e a28f200br 29 advance information 5.3 ac characteristics table 12. ac characteristics: read only operations (1) (automotive temperature) symbol parameter note min max unit t avav read cycle time 80 ns t avqv address to output delay 80 ns t elqv ce# to output delay 2 80 ns t phqv rp# to output delay 550 ns t glqv oe# to output delay 2 40 ns t elqx ce# to output in low z 3 0 ns t ehqz ce# to output in high z 3 20 ns t glqx oe# to output in low z 3 0 ns t ghqz oe# to output in high z 3 20 ns t oh output hold from address ce#, or oe# change whichever occurs first 300ns t elfl t elfh ce# low to byte high or low 3 5 ns t avfl address to byte# high or low 3 5 ns t flqv t fhqv byte# to output delay 3,4 80 ns t flqz byte# low to output in high z 330ns notes: 1. see ac input/output reference waveform for timing measurements. 2. oe# may be delayed up to t ce - t oe after the falling edge of ce# without impact on t ce . 3. sampled, but not 100% tested. 4. t flqv , byte# switching low to valid output delay will be equal to t avqv , measured from the time dq 15 /a -1 becomes valid. 5. see 5v standard test configuration. (figure 9)
a28f200br e 30 advance information address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v phqv t high z valid output data valid standby avav t ehqz t ghqz t oh t glqv t glqx t elqv t elqx t avqv t high z 0542_10 figure 9. ac waveforms for read operations address stable device address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# oe# byte# data (d/q) (dq0-dq7) ol v oh v high z data output on dq0-dq7 data valid standby avav t ehqz t ghqz t avqv t high z glqv t elqv t avqv t oh t data output on dq0-dq7 data (d/q) (dq8-dq14) ol v oh v high z data output on dq8-dq14 high z (dq15-a1) ol v oh v high z high z data output on dq15 address input flqz t elqx t elfl t avfl t glqx t 0542_11 figure 10. byte# timing diagram for both read and write operations with v cc at 5v
e a28f200br 31 advance information table 13. ac characteristics: we# Ccontrolled write operations (1) (automotivetemperature) symbol parameter notes min max unit t avav write cycle time 80 ns t phwl rp# high recovery to we# going low 450 ns t elwl ce# setup to we# going low 0 ns t phhwh boot block lock setup to we# going high 6,8 100 ns t vpwh v pp setup to we# going high 5,8 100 ns t avwh address setup to we# going high 3 60 ns t dvwh data setup to we# going high 4 60 ns t wlwh we# pulse width 60 ns t whdx data hold time from we# high 4 0 ns t whax address hold time from we# high 3 0 ns t wheh ce# hold time from we# high 10 ns t whwl we# pulse width high 20 ns t whqv1 duration of word/byte program operation 2,5 7 s t whqv2 duration of erase operation (boot) 2,5,6 0.4 s t whqv3 duration of erase operation (parameter) 2,5 0.4 s t whqv4 duration of erase operation (main) 2,5 0.7 s t qwl v pp hold from valid srd 5,8 0 ns t qvph rp# v hh hold from valid srd 6,8 0 ns t phbr boot-block relock delay 7,8 100 ns notes: 1. read timing characteristics during program and erase operations are the same as during read-onl y operations. refer to ac characteristics during read mode. 2. the on-chip wsm completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. refer to command definition table for valid a in . 4. refer to command definition table for valid d in . 5. program/erase durations are measured to valid srd data (successful operation, sr.7 = 1) 6. for boot block program/erase, rp# should be held at v hh or wp# should be held at v ih until operation completes successfully. 7. time t phbr is required for successful relocking of the boot block. 8. sampled, but not 100% tested. 9. v pp at 5v. 10. v pp at 12v. 11. see 5v standard test configuration.
a28f200br e 32 advance information addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v il v in d in a in a wheh t whwl t valid srd in d whqv1,2,3,4 t phhwh t ih v phwl t high z whdx t ih v il v v (v) pp 12 3 4 6 5 pph v pplk v pph v1 2 wp# il v ih v avav t avwh t whax t dvwh t wlwh t qvph t qvvl t vpwh t in d elwl t 0542_12 figure 11. ac waveforms for write operations (we#-controlled writes)
e a28f200br 33 advance information table 14. ac characteristics: ce# Ccontrolled write operations (1,12) symbol parameter notes min max unit t avav write cycle time 80 ns t phel rp# high recovery to ce# going low 450 ns t wlel we# setup to ce# going low 0 ns t phheh boot block lock setup to ce# going high 6,8 100 ns t vpeh v pp setup to ce# going high 5,8 100 ns t aveh address setup to ce# going high 60 ns t dveh data setup to ce# going high 3 60 ns t eleh ce# pulse width 4 60 ns t ehdx data hold time from ce# high 0 ns t ehax address hold time from ce# high 4 10 ns t ehwh we# hold time from ce# high 3 10 ns t ehel ce# pulse width high 20 ns t ehqv1 duration of word/byte program operation 2,5 7 s t ehqv2 duration of erase operation (boot) 2,5,6 0.4 s t ehqv3 duration of erase operation (parameter) 2,5 0.4 s t ehqv4 duration of erase operation (main) 2,5 0.7 s t qwl v pp hold from valid srd 5,8 0 ns t qvph rp# v hh hold from valid srd 6,8 0 ns t phbr boot-block relock delay 7,8, 100 ns notes: see we# controlled write operations for notes 1 through 11. 12. chip-enable controlled writes: write operations are driven by the valid combination of ce# and we# in systems where ce# defines the write pulse-width (within a longer we# timing waveform), all set-up, hold and inactive we# times should be measured relative to the ce# waveform.
a28f200br e 34 advance information addresses (a) we# (e) oe# (g) ce# (w) data (d/q) rp# (p) ih v il v ih v il v ih v il v ih v il v hh v 6.5v il v in d in a in a avav t in d valid srd in d qvph t phheh t high z ehdx t ih v il v v (v) pp 12 3 4 6 5 ehax t ehqv1,2,3,4 t ehel t ehwh t eleh t dveh t vpeh t qvvl t phwl t wlel t aveh t pplk v pph v1 2 pph v il v ih v il v ih v wp# 0542_13 figure 12. alternate ac waveforms for program and erase operations (ce#-controlled writes) table 15. extended temperature operations - erase and program timings parameter v pp = 5v 10% v pp = 12v 5% unit typ max typ max boot/parameter block erase time 0.8 7.8 0.34 4.0 s main block erase time 1.9 15.4 1.1 7.1 s main block write time (byte mode) 1.4 16.8 1.2 6.8 s main block write time (word mode) 0.9 8.4 0.6 3.4 s all numbers are sampled, not 100% tested.
e a28f200br 35 advance information appendix a ordering information b = bottom boot t = top boot product line designator for all intel flash products density / organization x00 = x8/x16 selectable(x = 2, 4, 8) access speed (ns) architecture b = boot block operating temperature a = automotive temp package b = psop voltage options (v pp ) r = (5 or 12) ab2 8 f2 0 0 br - t 8 0 0542_14 valid combinations: ab28f200br-t80 ab28f200br-b80
a28f200br e 36 advance information appendix b additional information (1,2) order number document 292130 ab-57 boot block architecture for safe firmware updates 292098 ap-363 extended flash bios concepts for portable computers 290448 28f002/200bx-t/b 2-mbit boot block flash memory datasheet 290449 28f002/200bl-t/b 2-mbit low power boot block flash memory datasheet 290450 28f004/400bl-t/b 4-mbit low power boot block flash memory datasheet 290451 28f004/400bx-t/b 4-mbit boot block flash memory datasheet 290531 2-mbit smartvoltage boot block flash memory family datasheet note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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